Hello! I am using TSE(triple speed ethernet) ip core to implement communication bewteen my pc and the FPGA(cyclone IV). But I don't know how to configure the TSE register with verilog. I do read some information from the user guide. For example, here are from the user guide:
| Base registers to configure the MAC function. At the minimum, you must configure the following functions: • Primary MAC address (mac_0/mac_1) • Enable transmit and receive paths (TX_ENA and RX_ENA bits in the command_config register) |
But I don't know how to realize this configuration in my project with verilog.
Anything can be help!
Best wishes!